A 90NM LOW POWER STATIC FLIP FLOP CONSISTING OF FIVE NORS AND TWO INVERTERS FOR DIGITAL VLSIS

P.Sathish Jogi Prakash

Abstract


In this article, we proposed a low power static flip-flop (LPSFF) for low power digital VLSIs. The design of the LPSFF consists of 24 transistors five NORs and two NOTs respectively. The LPSFF uses a positive edge of a buffered clock signal, which is generated from a reference clock, to take data into a master latch and a negative edge of the reference clock to hold the data in a slave latch. The LPSFF is same as like TBFF most commonly used in standard cell libraries. Cadence simulation setup for 90nm technology LPSFF achieved power- dissipation of 6.47 nW and clock to Q delay of 0.7543 µs at 0.35-V power supply and 1.1-2.0 MHz clock frequency. Our proposed LPSFF can operate at higher voltage like 0.5 V with power dissipation of 15.73 nW and delay of 253.5 ns, respectively.

Keywords: Low-Power Static Flip-Flop (LPSFF), Latch, Flip-Flop, Power and Delay


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References


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